FEATURES:

• PLDs) based on second-generation MAX architecture.
• 5.0-V in-system programmability (ISP) through the built-in IEEE Standard.
• ISP circuitry compatible with IEEE Std. 1532.
• Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices.
• Built-in JTAG boundary-scan test (BST) circuitry in MAX7000S devices with 128 or more macro cells.
• Complete EPLD family with logic densities ranging from 600 to 5,000 usable gates.
• 5-ns pin-to-pin logic delays with up to 175.4-MHz counter frequencies.

SPECIFICATIONS:

• Product: MAX 7000nbsp;
• Number of Macro cells: 64nbsp;
• Number of Logic Array Blocks LABs: 4nbsp;
• Maximum Operating Frequency: 151.5 MHz
• Propagation Delay Max:nbsp;        6 nsnbsp;
• Number of I/Os: 68 I/Onbsp;
• Operating Supply Voltage: 5 Vnbsp;
• Minimum Operating Temperature: 0 C
• Maximum Operating Temperature: + 70 C
• Package / Case: PLCC-84
• Memory Type:EEPROM
• Number of Gates: 1250

RELATED DOCUMENTS:

• Datasheet

PACKAGE INCLUDES:

• 1 X Altera EEPROM Based Programmable IC EPM7064SLC84-10 (CPLD – MAX 7000)